1. Field of the Invention
The present invention relates to insulated gate field effect transistors, and more particularly, to insulated gate field effect transistors having a high breakdown voltage and a low on-resistance.
2. Description of the Prior Art
Insulated gate field effect transistors (IGFET's) have become increasingly popular as circuit elements for various integrated circuits because their manufacturing is simple and their integration is easy. A major drawback of these transistors, however, has been their low breakdown voltage as measured between the drain and substrate is (40-50 V for P-channel MOS transistors and 20-30 V for N-channel MOS transistors). This low breakdown voltage is due to field concentration in the proximity of a drain region and a gate electrode or the like. As a result the field of application for IGFET's has been limited mainly to digital circuits which are operable in the voltage range of 5-15 V. With the growing use of MOS integrated circuits, the need for high drain voltage operations has been enhanced, and several techniques for making insulated gate field transistors having a high breakdown voltage have been developed.
For example, with regard of silicon high voltage P-channel insulated gate field effect transistors having an ion implanted offset gate structure, even those having a drain breakdown voltage of about 250-300 V have been obtained. These insulated gate field effect transistors have such structure that a pair of source and drain regions are provided in one major surface of a bulk silicon substrate, a gate insulator film is formed on the one major surface of the substrate between the source and drain regions, an extension drain region is formed in the one major surface of the substrate as extended from the drain region towards the source region, and a gate electrode is provided on the gate insulator film at the channel section between the extension drain region and the source region.
In such transistors, since the gate electrode and the high concentration drain region do not overlap with each other in a plan projection, field concentration can be mitigated. Furthermore, the extension drain region formed by ion implantation which is essentially a low concentration impurity region, is pinched off as the drain voltage applied to the drain region is increased, so that it serves as a saturating register. Accordingly, the divided voltage applied across the channel section can be suppressed to a low value, and so, the drain breakdown voltage is enhanced.
Therefore, in an insulated gate field effect transistor having, on its drain side, an offset gate structure consisting of an extension drain region and a bulk silicon substrate adjacent thereto, the drain breakdown voltage can be enhanced, in principle, up to the proximity of the PN junction breakdown voltage by selecting the offset gate length (i.e., the length of the extension drain region) sufficiently long. The PN junction breakdown voltage is determined by the impurity concentration of the bulk silicon substrate.
However, in order to attain a still higher breakdown voltage using a transistor with the above-described structure, it is necessary to greatly sacrifice an "on-resistance" (a series resistance between a source and a drain when a transistor is in a conducting state). As a result of the foregoing the high breakdown voltage and the low on-resistance are mutually complicting factors.
On one hand it is desired that the impurity concentration of the substrate is as low as possible to increase the PN junction breakdown voltage between the drain region and the substrate. On the other hand, it is desirable to have a high ion dose implanted to the extension drain region (that is, the impurity concentration and distribution in said region as measured in the direction of the film thickness) since the ion dose determines the on-resistance of the transistor. However, since it is necessary that upon increase of the drawin voltage the extension drain region serving as a saturating resistor must be pinched off before the divided voltage that is applied across the effective MOS channel section reaches its insulation breakdown voltage (for instance; 40-80 V), the upper limit of the amount of electrically active impurities per unit area which can be doped into said region is determined by the impurity concentration of the bulk silicon substrate. In other words, the offset gate type transistors in the prior art had a disadvantage that if the impurity concentration of the substrate is lowered for attaining a high breakdown voltage of the transistor, then at the same time the ion dose implanted to the extension drain region must be also suppressed. Furthermore, since punch-through between the source and the drain becomes liable to occur by employing a low impurity concentration substrate, it is necessary to make the effective MOS channel section gate length sufficiently long to the extent of, for example, 16-20 .mu.m, and so, the on-resistance at the effective MOS channel section also cannot be lowered.
Still further, in the case of N-channel insulated gate field effect transistors which necessitate a high substrate impurity concentration for an enhancement operation, realization of high voltage transistors having an offset gate structure was difficult. For instance, assuming that an impurity concentration of an N-type bulk silicon substrate is (5-7).times.10.sup.14 cm.sup.-3, P.sup.+ -ype source and drain regions having an impurity concentration of 10.sup.19 -10.sup.20 cm.sup.-3 are formed in the substrate at a depth of 2.4 .mu.m, a P-type extension drain region of 30 .mu.m in length and 0.4 .mu.m in depth is provided with an impurity concentration 2.times.10.sup.16 cm.sup.-3, and a channel length is selected to be 20 .mu.m. Then a breakdown voltage of 250-300 V can be obtained, but a sheet resistivity R.quadrature. in the extension drain region becomes as high as 20 K.OMEGA./.quadrature.-26 K.OMEGA./.quadrature., and therefore an on-resistance Ron of the transistor becomes a high level. On the other hand, if the impurity concentration of the extension drain region is selected to be, for example, 4.times.10.sup.16 cm.sup.-3 for the purpose of lowering the ON-resistance, the the sheet resistivity R.quadrature. of the extension drain region can be lowered to 10 K.OMEGA./.quadrature.-16 K.OMEGA./.quadrature.. However, in this case, in view of the necessity for the inherent operation of the offset gate structure transistors that the extension drain region must be pinched off before the divided voltage which is applied across the MOS channel section reaches the insulation breakdown voltage of that section, the impurity concentration of the bulk silicon substrate must be 3.times.10.sup.15 cm.sup.-3 or higher. Accordingly, the breakdown voltage takes a value of 100 V or lower, and no longer the transistor can be a high voltage MOS EFT.
In addition, the above-described prior art in which the substrate impurity concentration must be selected as low as (5-7).times.10.sup.14 cm.sup.-3, is not adaptive to the N-channel NOS FET. If it is necessary to attain a further enhanced breakdown voltage, it is required to further lower the impurity concentration of the substrate, and thus it is necessitated to suppress the ion does implanted to the offset gate section to a lower value and to select the MOS gate length longer, so that the on-resistance of the insulated gate field effect transistors is inevitably raised. Such an offset gate type transistor in the prior art is disclosed, for example, in "Proceedings of the 6th Conference on Solid State Devices, Tokyo, 1974" Supplement to the Journal of the Japan Society of Applied Physics, Vol. 44, 1975 pp. 249-255.